The present invention relates to integrated circuits, and more particularly, to semiconductor memory devices.
Three types of silicon integrated memory devices may be distinguished. A first type is a DRAM (Dynamic Random Access Memory) type memory made up of dynamic memory locations. A DRAM includes elementary cells which are read and written to individually. These cells are compact since they are generally composed of a transistor and a capacitor. They have a short access time, typically about 40 to 60 ns, but the stored information must be frequently refreshed.
A second type is an SRAM (Static Random Access Memory) type memory made up of static memory locations. An SRAM includes elementary cells which are addressed both in a read mode and in a write mode. Moreover, they have a short cycle time with access times of about 6 to 70 ns. Furthermore, they retain the information as long as they are supplied power. However, these cells remain limited by their low density, since in general, they are made up of six transistors.
A third type is known as non-volatile memories, for example, flash memories which can retain information for several years within a floating gate which is electrically isolated, for example, by oxide, and do so without being refreshed or supplied. This type of memory is compact since the cells of which they are composed are in general formed from a single transistor. However, the write mechanism, based on the tunnel effect through the isolation oxide of the floating gate, is slow and requires high bias voltages. This results in access times possibly as long as one millisecond. Moreover, these cells cannot typically be addressed for the purpose of erasing them.
In view of the foregoing background, an object of the present invention is to provide an integrated semiconductor memory device offering hybrid performance by combining the performance of a conventional flash cell with that of a conventional DRAM cell, while overcoming their respective limitations.
Another object of the present invention is to provide a memory location which is erase/write addressable, while having the compactness of a single transistor. Moreover, the read/write mode of the memory location according to the present invention furthermore allows an information access time of a few nanoseconds, since writing to the cell uses transfer mechanisms based on so-called xe2x80x9cdriftxe2x80x9d currents which are much more rapid than the tunnel effect used in flash technology.
The basic principle of the invention relies on the confinement of a charge (a negative charge, i.e., electrons, or a positive charge, i.e., holes) in one of the two potential wells separated by a field-effect barrier. The basic structure of the memory device according to the invention is therefore a kind of xe2x80x9cisolated switchxe2x80x9d having two states. The state depends on which potential well zone has the charge.
In other words, according to a general feature of the invention, the integrated semiconductor memory device comprises an integrated memory location structure having an isolating-envelope-embedded semiconductor layer (isolated switch) lying between the source region and the drain region of a transistor, and inserted between the channel region of the transistor and its control gate. This isolated semiconductor layer includes two potential well zones separated by a potential barrier zone lying beneath the control gate of the transistor.
The semiconductor memory device according to the invention may also comprise write means or write circuitry for biasing the memory location structure so as to confine charge carriers selectively in one of the two potential well zones.
The device may also comprise read means or read circuitry for biasing the memory location structure so as to detect the presence of charge carriers in one of the potential wells, and thus allows the logic 0 or logic 1 state of the switch to be detected. This detection can take place in various ways, for example, simply by measuring the drain current of the transistor and consequently, indirectly measuring the threshold voltage of the device. This is because the position of the charge carriers in one of the potential wells exerts an electrical effect on the transistor drain current sufficient to distinguish the two states, i.e., logic 0 and logic 1, in the read mode.
In a first variation of the invention, the isolated semiconductor layer may include a central zone having the same type of conductivity (for example, p-type conductivity) as that of the source and drain regions of the transistor (for example, a PMOS transistor). This central zone forms the potential barrier zone. The isolated semiconductor layer also includes two outer zones lying respectively on either side of the central zone, and having the same type of conductivity but different from that of the central zone. These two outer zones may, for example, be n-doped and respectively form the two potential well zones.
In another variation of the invention, the isolated semiconductor layer may be undoped, formed for example, from intrinsic silicon. The memory location structure then includes two auxiliary gates placed respectively on either side of the control gate of the transistor. These two auxiliary gates are isolated from this control gate and have the same type of conductivity, but different from that of the control gate. Thus, if the control gate is p+-doped, the two auxiliary gates will be n+-doped. The two potential well zones lie beneath the two auxiliary gates and are electrostatically induced by the latter, whereas the potential barrier zone is electrostatically induced by the control gate.
According to one embodiment of the invention, and regardless of the variation used, the write means may bias the control gate and the source and drain electrodes to confine charge carriers selectively in one of the two potential well zones. More specifically, according to one embodiment, the write means may bias the source or drain electrode to confine the charge carriers, then bias the control gate to eliminate the potential barrier between the two potential wells, then in unbiasing the control gate and finally in unbiasing the electrode. Thus, the write means allow the charge carriers, for example, electrons, to pass from one electrode to the other.
According to one embodiment of the invention, the read means may bias the control gate, and if necessary, the two auxiliary gates with a bias voltage opposite to that used by the write means. The subject of the invention is also an integrated circuit comprising at least one integrated memory device as defined above.
The invention also provides a process for fabricating an integrated semiconductor memory device, comprising the fabrication of an MOS transistor, and the fabrication of an isolating-envelope-embedded semiconductor layer lying between the source and drain regions of the transistor and inserted between the channel region of the transistor and its control gate. This isolated semiconductor layer may include two potential well zones separated by a potential barrier zone lying beneath the control gate of the transistor.
According to a first variation of the invention, the fabrication of the isolated semiconductor layer comprises an epitaxial growth on a silicon substrate having a first type of conductivity, of a first layer formed from a material selectively removable with respect to silicon, for example, a silicon-germanium alloy. An epitaxial growth is on the first layer and includes a silicon semiconductor second layer having a second type of conductivity. A surface isolating layer may be formed on the second layer.
Moreover, the fabrication of the transistor comprises the production, on the surface isolating layer, of a semiconductor region for the control gate having the second type of conductivity.
The fabrication of the isolated semiconductor layer (isolated switch) furthermore comprises the implantation of dopants in the semiconductor second layer on either side of the gate region to form, in this semiconductor second layer, a central zone having the same type of conductivity as that of the source and drain regions of the transistor and forming the potential barrier zone. Two outer zones lie respectively on either side of the central zone, and have the same type of conductivity but different from that of the central zone, and respectively form the two potential well zones.
The fabrication further includes the etching of the surface isolating layer, the semiconductor second layer, the first layer and part of the substrate, on either side of the gate region flanked by isolating spacers. The first layer is selectively removed to form a tunnel, and the tunnel is filled with an insulating material. The fabrication also includes the formation of a lateral isolating layer on the sidewalls of the semiconductor second layer.
The filling of the tunnel may take place by conformal deposition of oxide. Moreover, the formation of the lateral isolating layer may comprise silicon oxidation followed by anisotropic plasma etching of the oxide thus formed.
According to one method of implementing the invention, the fabrication of the transistor includes the epitaxial growth of the source and drain regions in the substrate on either side of the laterally isolated semiconductor second layer (isolated switch).
According to another variation of the invention, compatible with a double-gate device, the fabrication of the isolated semiconductor layer comprises the epitaxial growth, on a silicon substrate having a first type of conductivity, of a first layer formed from a material selectively removable with respect to silicon, for example, a silicon-germanium alloy. The fabrication also includes the epitaxial growth, on the first layer, of an undoped silicon semiconductor second layer, and the formation of a surface isolating layer on the second layer.
Moreover, the fabrication of the transistor includes the production, on the surface isolating layer, of a semiconductor control gate region having a second type of conductivity.
The fabrication of the isolated semiconductor layer furthermore includes the formation of two auxiliary gates placed respectively on either side of the control gate of the transistor. These auxiliary gates are isolated from this control gate and have the same type of conductivity but different from that of the control gate. The two potential well zones lie beneath the two auxiliary gates and are induced electrostatically by the latter, whereas the potential barrier zone is induced electrostatically by the control gate.
The fabrication may also include etching of the surface isolating layer, the semiconductor second layer, the first layer and part of the substrate, respectively on either side of the assembly formed by the control gate and the two auxiliary gates which are flanked by isolating spacers. The first layer is selectively removed to form a tunnel, and the tunnel is filled with an insulating material. A lateral isolating layer is formed on the sidewalls of the semiconductor second layer.
The formation of the control gate and the formation of the two auxiliary gates comprise, for example, the deposition of a layer of a first semiconductor gate material having a second type of conductivity, for example p-type; the anisotropic etching of the layer of gate material so as to form a block; and the formation of two symmetrical lateral recesses in the block. An isolating layer is formed on the walls of the recesses, and the two recesses are filled, and are coated with the isolating layer with a second gate material having the first type of conductivity, for example, n-type.
The auxiliary gates formed in this way are consequently self-aligned with respect to the control gate. The formation of the lateral recesses comprises, for example, thermal oxidation of the block followed by wet etching of the oxide formed. Again, in this variation, the filling of the tunnel may be carried out by conformal deposition of oxide, whereas the formation of the lateral isolating layer may be carried out by silicon oxidation followed by anisotropic plasma etching of the oxide. The fabrication of the transistor may also include in this variation the epitaxial growth of the source and drain regions in the substrate on either side of the laterally isolated semiconductor second layer.
In another variation of the invention, also compatible with a device having two control gates, the isolated semiconductor layer may result from deposition on an insulating layer obtained, for example, by thermal oxidation of the substrate. More specifically, according to such a variation, the fabrication of the isolated semiconductor layer comprises the formation of an isolating first layer on a silicon substrate having a first type of conductivity; the deposition of an undoped semiconductor second layer on the isolating first layer; and the formation of a surface isolating layer on the second layer.
The fabrication of the transistor again includes the production, on the surface isolating layer, of a semiconductor control gate region having a second type of conductivity. The fabrication of the isolated semiconductor layer (isolated switch) may furthermore include the formation of two auxiliary gates placed respectively on either side of the control gate of the transistor. These auxiliary gates are isolated from this control gate and have the same type of conductivity but different from that of the control gate. The two potential well zones lie beneath the two auxiliary gates and are induced electrostatically by the latter, whereas the potential barrier zone is induced electrostatically by the control gate.
The fabrication also includes etching of the surface isolating layer and the semiconductor second layer, respectively on either side of the assembly formed by the control gate and the two auxiliary gates which are flanked by isolating spacers. A lateral isolating layer is formed on the sidewalls of the semiconductor second layer.
According to one method of implementation compatible with this variation, the fabrication of the transistor may include the anisotropic etching of the isolating first layer on either side of the isolated semiconductor layer to expose the substrate, and the epitaxial growth of the source and drain regions in the substrate on either side of the laterally isolated semiconductor second layer (isolated switch).